- When: December 2 – 4, 2020
- Where: Singapore
The 22nd Electronics Packaging Technology Conference (EPTC) is an International event organized by the IEEE RS/EPS/EDS Singapore Chapter and sponsored by the IEEE Electronics Packaging Society (EPS). Since its inauguration in 1997, EPTC has developed into a highly reputed electronics packaging conference in the Asia-Pacific region and is well attended by experts in all aspects of packaging technology from all over the world. It is a major forum for the exchange of knowledge and experience in electronics packaging and provides opportunities to network and meet with leading international experts. The technical sessions cover the whole range of electronics packaging including the following areas:
- Advanced Packaging: Advanced Flip-chip, 2.5D & 3D, PoP, embedded passives & actives on substrates, System in Packaging, embedded chip packaging technologies, Panel level packaging, RF, Microwave & Millimeter-wave, Power and Rugged Electronics Packaging etc.
- TSV/Wafer Level Packaging: Wafer level packaging (Fan in/Fan out), embedded chip packaging, 2.5D/3D integration, TSV, Silicon & Glass interposer, RDL, bumping technologies, etc.
- Interconnection Technologies: Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar, solder alternatives (ICP, ACP, ACF, NCP, ICA), Cu to Cu, Wafer level bonding & die attachment (Pb-free) etc.
- Emerging Technologies: Packaging technologies for MEMS, biomedical, optoelectronics, Internet of things, photo voltaic, printed electronics, wearable electronics, Photonics, LED, etc.
- Materials and Processing: advanced materials such as 2D materials, photoresist, polymer dielectrics, solder materials, die attach, underfill, Substrates, Lead-frames, PCB etc for advanced packaging, and assembly processes using advanced materials
- Equipment and Process Development & Automation: processes development, equipment automation, process and equipment hardware improvements, data analytics, in-situ metrology.
- Electrical Simulation & Characterization: Power plane modeling, signal integrity analysis by simulations and characterization. 2D/2.5D/3D package level high-speed signal design, characterization and test methodologies.
- Mechanical Simulation & Characterization: Thermo-mechanical, moisture, fracture, fatigue, vibration, Shock and drop impact modeling, chip-package interaction, etc.
- Thermal Characterization & Cooling Solutions: Thermal modeling and simulation, component, system and product level thermal management and characterization
- Quality, Reliability & Failure Analysis: Component, board, system and product level reliability assessment, Interfacial adhesion, accelerated testing, failure characterization, etc.
Read more at: https://eps.ieee.org/conferences.html